A magnetic memory cell may store information by changing electrical resistance of a magnetic tunnel junction (MTJ) element. The MTJ element typically includes a thin insulating tunnel barrier layer sandwiched between a magnetically fixed layer and a magnetically free layer, forming a magnetic tunnel junction. Magnetic orientations of the fixed and free layers may be perpendicular to the growth direction, forming a perpendicular MTJ (or pMTJ) element.
Spin transfer torque (STT) or spin transfer switching, uses spin-aligned (“polarized”) electrons to directly apply a torque on the MTJ layers. Specifically, when electrons flowing into a layer have to change spin direction, a torque is developed and is transferred to the nearby layer.
Magnetic memory cells are typically provided as addressable bit cells in an array of columns and rows. Such an array is provided with corresponding source lines, bit lines and word lines to perform operations on selected bit cells. Typically, each column of memory cells is provided with a dedicated source line and a dedicated bit line. As technology scales, there is difficulty in reducing the amount of chip area and height used by such memory cell arrays.
In view of the foregoing, it is desirable to provide an integrated circuit having memory cells that use a reduced amount of chip area and/or height, as compared to conventional layouts. Furthermore, it is also desirable to provide a memory array in which certain adjacent columns of memory cells share a bit line and other adjacent columns of memory cells share a source line. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.